1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a driving apparatus and apparatus for a liquid crystal display wherein an NTSC (National Television System Committee) signal can be selectively converted in response to an instruction of a user.
2. Discussion of the Related Art
Generally, an active matrix liquid crystal display (LCD) uses thin film transistors (TFT's) as switching devices to display a moving picture. Because such a LCD can be made smaller in size than related art cathode-ray tubes, LCDs have been widely used as monitors for personal computers or notebook computers as well as office automation equipment such as copy machines and portable equipment such as cellular phones and pagers.
The active matrix LCD displays a picture corresponding to video signals, such as television signals, on a picture element matrix or pixel matrix having liquid crystal cells arranged at crossings of gate lines and data lines. The thin film transistor is provided at each crossing between the gate lines and the data lines to switch a data signal to be transmitted into the liquid crystal cell in response to a scanning signal (or gate pulse) from the gate line.
Such an LCD is classified as one for displaying NTSC signals and one for PAL signals in accordance with the television signal system in the area in which the LCD is used.
Generally, if an NTSC signal (i.e., 525 vertical lines) is received, then a horizontal resolution of the LCD is expressed in accordance with sampled data while a vertical resolution thereof is expressed by a 234 line de-interlaced scheme. On the other hand, if a PAL signal (i.e., 625 vertical lines) is received, then a horizontal resolution of the LCD is expressed in accordance with sampled data while a vertical resolution thereof is expressed by a processing system similar to the NTSC signal scheme in which one line is removed for each six vertical lines to be resulted in 521 lines.
Referring to FIG. 1, a related art LCD driving apparatus includes a liquid crystal display panel 30 having liquid crystal cells arranged in a matrix type, a gate driver 34 for driving gate lines GL of the liquid crystal display panel 30, a data driver 32 for driving data lines DL of the liquid crystal display panel 30, an image signal processor 10 for converting an NTSC image signal input into a voltage suitable for driving the liquid crystal display panel 30 and for outputting a complex synchronizing signal' a format signal generator 22 that generates a format signal converted for display on the liquid crystal display panel 30, and a timing controller 20 for receiving the complex synchronizing signal from the image signal processor 10 to separately output a horizontal synchronizing signal Hsync and a vertical synchronizing signal Vsync and for controlling the gate driver 34 and the data driver 32 in response to format signals M1, M2 and M3 from the format signal generator 22.
The image signal processor 10 converts an NTSC image signal into a signal suitable for driving the liquid crystal display panel 30, and applies the complex synchronizing signal to the timing controller 20.
The liquid crystal display panel 30 includes liquid crystal cells arranged in a matrix and thin film transistors TFT at the crossing of the gate lines GL and the data lines DL connected to the liquid crystal cells.
The thin film transistor TFT is turned on when a scanning signal, i.e., a gate high voltage VGH from the gate line GL, is applied, and applying a pixel signal from the data line DL to the liquid crystal cell. On the other hand, the thin film transistor TFT is turned off when a gate low voltage VGL is applied from the gate line GL, maintaining a pixel signal charged in the liquid crystal cell.
The liquid crystal cell can be equivalently expressed as a liquid crystal capacitor LC, and includes a pixel electrode connected to a common electrode and the thin film transistor TFT that are opposite each other having a liquid crystal therebetween. Further, the liquid crystal cell includes a storage capacitor Cst for maintaining the charged pixel signal until the next pixel is charged. This storage capacitor Cst is provided between a pre-stage gate line and the pixel electrode. Such an liquid crystal cell varies the alignment state of the liquid crystal having a dielectric anisotropy in response to the pixel signal charged via the thin film transistor TFT to control light transmittance, thereby implementing a gray scale level.
The gate driver 34 sequentially applies the gate high voltage VGH to the gate lines GL in response to gate control signals GSP, GSC and GOE from the timing controller 20. Thus, the gate driver 34 drives the thin film transistors TFT connected to the gate lines GL for each gate line.
More specifically, the gate driver 34 shifts a gate start pulse GSP in response to a gate shift pulse GSC, thereby generating a shift pulse. Further, the gate driver 34 applies the gate high voltage VGH to the corresponding gate line GL every horizontal period H1, H2, . . . in response to the shift pulse. In this case, the gate driver 34 applies the gate high voltage VGH only in an enable period in response to a gate output enable signal GOE. On the other hand, the gate driver 34 applies the gate low voltage VGL in the remaining period when the gate high voltage VGH is not applied to the gate lines GL.
The data driver 32 applies pixel data signals to the data lines DL for each line in every horizontal period 1H, 2H, . . . in response to data control signals SSP, SSC and SOE from the timing controller 20. Particularly, the data driver 32 applies RGB data from the image signal processor 10 to the liquid crystal display panel 30.
More specifically, the data driver 32 shifts a source start pulse SSP in response to a source shift clock SSC to generate a sampling signal. Then, the data driver 32 sequentially inputs analog RGB data for each certain unit in response to the sampling signal to latch them. Further, the data driver 32 applies the latched analog data for one line to the data lines DL.
As shown in FIG. 2, the format signal generator 22 includes a first format signal generator 22a having first and second switches SW1 and SW2 connected in series between a voltage source Vcc and a ground voltage source GND, a second format signal generator 22b having third and fourth switches SW3 and SW4 connected in series between the voltage source Vcc and the ground voltage source GND, and a third format signal generator 22c having fifth and sixth switches SW5 and SW6 connected in series between the voltage source Vcc and the ground voltage source GND.
The format signal generator 22 applies a high-level voltage Vcc from the voltage source Vcc or a ground voltage GND from the ground voltage source GND under switching of each of the first to sixth switches SW1 to SW6 in response to a switching control signal. Herein, the switching control signal is set in advance by a system engineer.
More specifically, the first format signal generator 22a applies a first format signal M1 having a high level to a first format signal input terminal at the timing controller 20 when only the first switch SW1, of the first and second switches SW1 and SW2, is turned on while applying a first format signal M1 having a ground level to the first format signal input terminal at the timing controller 20 when only the second switch SW2 is turned on. Likewise, the second format signal generator 22b applies a second format signal M2 having a high level to a second format signal input terminal at the timing controller 20 when only the third switch SW3, of the third and fourth switches SW3 and SW4, is turned on while applying a second format signal M2 having a ground level to the second format signal input terminal at the timing controller 20 when only the fourth switch SW4 is turned on. Further, the third format signal generator 22c applies a third format signal M3 having a high level to a third format signal input terminal at the timing controller 20 when only the fifth switch SW5, of the fifth and sixth switches SW5 and SW6, is turned on while applying a third format signal M3 having a ground level to the third format signal input terminal at the timing controller 20 when only the sixth switch SW6 is turned on.
The timing controller 20 separates a horizontal synchronizing signal H and a vertical synchronizing signal V from the complex synchronizing signal from the image signal processor 10 to apply them to the data driver 32. Further, the timing controller 20 sets a format of an image signal displayed on the liquid crystal display panel 30 in response to the format signals M1, M2 and M3 from the format signal generator 22, and generates control signals for controlling a driving timing of each of the gate driver 34 and the data driver 32 in accordance with the set format. In other words, the timing controller 20 generates gate control signals GSP, GSC and GOE in response to the format signals M1, M2 and M3 from the format signal generator 22 to control the gate driver 34, and generates data control signals SSP, SSC and SOE to control the data driver 32.
More specifically, the timing controller 20 combines the first through third format signals M1, M2 and M3 from the format signal generator 22 to thereby set a format of the image signal displayed on the liquid crystal display panel 30, and generates and supplies control signals for controlling a driving timing of each of the gate driver 34 and the data driver 32 in accordance with the set format of the image signal. The timing controller 20 combines the first through third format signals M1, M2 and M3 from the format signal generator 22 and selects any one of a plurality of image formats indicated by Table 1 in accordance with a logical value obtained by the above-mentioned combination.
TABLE 1M1M2M3Image Format00010012010301141005101611071118
In Table 1, the first through eighth image formats have corresponding values in which the number of data lines and the number of gate lines required to display an image signal on the liquid crystal display panel are different.
In such an LCD driving apparatus and method, any one of a plurality of image formats is selected from the timing controller 20 in response to a switching of each switch SW1 to SW6 of the format signal generator 22 that are set in advance by a system engineer. Thus, the timing controller 20 controls each of the gate driver 34 and the data driver 32 in accordance with the selected image format. Accordingly, an image format selected by the timing controller 20 is displayed on the liquid crystal display panel 30.
The related art LCD driving apparatus and method has a problem in that, because a switching control signal for each switch SW1 to SW6 of the format signal generator 22, used to select an image format for display on the liquid crystal display panel 30, is set in advance by a system engineer, the image format can not be changed in accordance with a user's preference.